An efficient FPGA priority queue implementation with application to the routing problem

The FPGA-QQ (Field Programmable Gate Array Quick Queue) is a novel, efficient priority queue implementation targeted specifically for FPGAs. This paper describes its architecture and use in acceleration of the FPGA routing problem. FPGA-QQ utilizes the FPGA’s blocks of on-chip memory to store keys and values in a completely ordered fashion. The use of the on-chip block memory allows hundreds to thousands of items to be held in the queue at any given time, more than any other published design for an FPGA implementation. The queue is formed by a series of cascadable nodes. The latency of the queue is (roughly) equivalent to the depth of the RAM in a given node. This implementation is then applied to accelerate the routing phase of a standard FPGA CAD flow. Results are positive and speedups grow with the size of the queue up to (and possibly beyond) 16× faster than a standard software heap. keywords: FPGA, routing, priority queue, hardware acceleration ∗Supported by a Cota-Robles Fellowship. Thanks for lab support and guidance from Professor Pak Chan.